Silhueta de pessoa indiferenciada

Jorge Filipe Leal Costa Semião

Professor Adjunto
Instituto Superior de Engenharia
Subsistema
Orgãos de Gestão
Unidade ID externa
Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa (INESC-ID)
Regime
Exclusividade
Vínculo
CT em Funções Públicas por tempo indeterminado

Atividades

Atividades
2020 - 2020. Orientação. PERFORMANCE SENSOR FOR CMOS MEMORY CELLS - SENSOR DE PERFORMANCE PARA CÉLULAS DE MEMÓRIA CMOS.Engenharia Eletrotécnica e de Computadores (Mestrado). Orientador.
2018 - 2018. Orientação. Automatic Analysis of Subthreshold Operation in CMOS Digital Circuits.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2016 - 2016. Orientação. Projeto de soluções confiáveis de automação em ambiente industrial .Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2016 - 2016. Orientação. AGING SENSOR FOR CMOS MEMORY CELLS.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2015 - 2015. Orientação. SISTEMA REMOTO PARA MONITORIZAÇÃO DE AMBIENTES REFRIGERADOS EM VIATURAS AUTOMÓVEIS.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2015 - 2015. Orientação. SISTEMA DE AQUISIÇÃO PARA MONITORIZAÇÃO DA PRODUÇÃO DE ENERGIA EM SISTEMAS DE ENERGIA RENOVÁVEL.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2014 - 2014. Orientação. Aging monitoring methodology for built-In self-test applications Metodologia de monitorização do envelhecimento para aplicações de auto-teste embutido.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2013 - 2013. Orientação. Dynamic power and frequency optimization in digital electronic systems.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.
2012 - 2012. Orientação. METODOLOGIA PARA PREVER O ENVELHECIMENTO DE CIRCUITOS DIGITAIS.Engenharia Eléctrica e Electrónica (Mestrado). Orientador.

Projetos

Projetos
2009/01/01 - 2012/03/31. Nanoelectrónica para aplicações na indústria automovel SE2A, 3599-PPCDT. INESC Microsistemas e Nanotecnologias; INOV INESC INOVAÇÃO - Instituto de Novas Tecnologias; Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa.
2006/01/01 - 2009/12/31. METODOLOGIAS BASEADAS NA TENSÃO DE ALIMENTAÇÃO E TEMPERATURA PARA MELHORAR A TOLERÂNCIA E A DETECÇÃO DE FALTAS DINÂMICAS EM SISTEMAS INTEGRADOS DIGITAIS, POSI.
2005/01/01 - 2008/03/31. Teste Dinâmico de Sistemas Integrados em Nanotecnologias, POSC. Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa; Universidade do Algarve.
2006/09/01 - 2007/10/31. Colaboração na Experiência CMS no CERN, POCI. Laboratório de Instrumentação e Física Experimental de Partículas Coimbra; Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa.
2005/08/01 - 2006/09/30. Colaboração na Experiência CMS no CERN, POCI. Laboratório de Instrumentação e Física Experimental de Partículas Coimbra; Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa.

Produções

Pedro J. S. Cardoso; Jânio Monteiro; Cristiano Cabrita; Jorge Semião; Dario Medina Cruz; Nelson Pinto; Célia M.Q. Ramos; Luís M. R. Oliveira; João M. F. Rodrigues. 2021. "Monitoring, Predicting, and Optimizing Energy Consumptions". Em A Goal Toward Global Sustainability, 20-47. {IGI. https://doi.org/10.4018/978-1-7998-9152-9.ch002
J. Semião; H. Santos; R. Cabral; M. B. Santos; P. Teixeira. 2020. "PVTA-Aware Performance SRAM Sensor for IoT Applications". https://doi.org/10.1007/978-3-030-30938-1_27
Litrán, Salvador P.; Durán, Eladio; Semião, Jorge; Barroso, Rafael S.. 2020. "Single-switch bipolar output DC-DC converter for photovoltaic application". https://doi.org/10.3390/electronics9071171
Santos, Luís Mário Braz dos. 2020. "Performance sensor for CMOS memory cells". Mestrado. http://hdl.handle.net/10400.1/15380
Sartelli, Massimo; Abu-Zidan, Fikri M.; Labricciosa, Francesco M.; Kluger, Yoram; Coccolini, Federico; Ansaloni, Luca; Leppäniemi, Ari; et al. 2019. "Physiological parameters for Prognosis in Abdominal Sepsis (PIPAS) Study: a WSES observational study". https://doi.org/10.1186/s13017-019-0253-2
J. D. Mozo; J. I. Otero; E. Durán; Jorge Semião. 2018. "An Open Hardware Electronic Controller for Motorized Rotary Injection Valves Used in Flow Injection Analysis". 259-267. Springer International Publishing. https://doi.org/10.1007/978-3-319-70272-8_22
Cavalaria, Hugo Alexandre Nunes. 2018. "Automatic analysis of subthreshold operation in CMOS digital circuits". Mestrado. http://hdl.handle.net/10400.1/10972
Mozo, J. D.; Otero, J. I.; Durán, E.; Semião, Jorge. 2018. "An open hardware electronic controller for motorized rotary injection valves used in Flow Injection Analysis". https://doi.org/10.1007/978-3-319-70272-8_22
Sardo, João Duarte Pereira. 2017. "Portable device for augmented reality: five-sense experiences". Mestrado. http://hdl.handle.net/10400.1/10402
Cardoso, PJS; Schuetz, G; Semiao, J; Monteiro, J; Rodrigues, J; Mazayev, A; Ey, E; Viegas, M. 2016. "Integration of a Real-Time Stochastic Routing Optimization Software with an Enterprise Resource Planner". https://doi.org/10.1007/978-3-319-29589-3_8
Santos, H; Semiao, J; Cabral, R; Romao, A; Santos, MB; Teixeira, IC; Teixeira, JP. 2016. "Aging and Performance Sensor for SRAM". https://doi.org/10.1109/dcis.2016.7845354
Costa, Hugo Miguel Conceição. 2016. "Sistema de monitorização e previsão inteligente de consumos elétricos". Mestrado. http://hdl.handle.net/10400.1/8306
Cardoso, Pedro J. S.; Schuetz, Gabriela; Semiao, Jorge; Monteiro, Janio; Rodrigues, Joao; Mazayev, Andriy; Ey, Emanuel; Viegas, Micael. 2016. "Integration of a real-time stochastic routing optimization software with an enterprise resource planner". https://doi.org/10.1007/978-3-319-29589-3_8
Conceição, Abel Jorge Gonçalves da. 2016. "Projeto de soluções confiáveis de automação em ambiente industrial". Mestrado. http://hdl.handle.net/10400.1/9851
Santos, Hugo Fernandes da Silva. 2016. "Aging sensor for CMOS memory cells". Mestrado. http://hdl.handle.net/10400.1/8028
Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP. 2015. "Fault-Tolerance in FPGA Focusing Power Reduction or Performance Enhancement". https://doi.org/10.1109/latw.2015.7102523
Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP; Batista, AJN; Goncalves, B; Marques, JG. 2015. "Fast Radiation Monitoring in FPGA-based Designs". https://doi.org/10.1109/dcis.2015.7388590
Leong, C; Semiao, J; Santos, MB; Teixeira, IC; Teixeira, JP. 2015. "Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling". JOURNAL OF LOW POWER ELECTRONICS. https://doi.org/10.1166/jolpe.2015.1406
Vasconcelos, Sérgio Ricardo Martins. 2015. "Sistema remoto para monitorização de ambientes refrigerados em viaturas automóveis". Mestrado. http://hdl.handle.net/10400.1/7916
Semiao, J; Leong, C; Romao, A; Santos, MB; Teixeira, IC; Teixeira, JP. 2014. "Aging-aware dynamic voltage or frequency scaling". https://doi.org/10.1109/dcis.2014.7035599
Tinoco, Mário Jorge de Aguiar Laranjo. 2014. "Sistema de aquisição para monitorização da produção de energia em sistemas de energia renovável". Mestrado. http://hdl.handle.net/10400.1/8372
Semião, Jorge. 2013. "Aging Monitoring with Local Sensors in FPGA-based Designs". https://doi.org/10.1109/FPL.2013.6645596
Leong, C; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP; Valdes, M; Freijedo, J; Rodriguez Andina, JJ; Vargas, F. 2013. "AGING MONITORING WITH LOCAL SENSORS IN FPGA-BASED DESIGNS". https://doi.org/10.1109/fpl.2013.6645596
Valdes-Pena, M.D.; Fernandez Freijedo, J.; Moure Rodriguez, M.J.; Rodriguez-Andina, J.J.; Semiao, J.; Teixeira, I.M.C.; Teixeira, J.P.C.; Vargas, F.. 2013. "Design and validation of configurable online aging sensors in nanometer-scale FPGAs". IEEE Transactions on Nanotechnology, 12 (4): 508-517. https://doi.org/10.1109/TNANO.2013.2253795
Vazquez, J.C.; Champac, V.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. 2013. "Process variations-aware statistical analysis framework for aging sensors insertion". Journal of Electronic Testing: Theory and Applications (JETTA), 29 (3): 289-299. https://doi.org/10.1007/s10836-013-5358-z
Valdes Pena, MD; Fernandez Freijedo, JF; Moure Rodriguez, MJM; Rodriguez Andina, JJ; Semiao, J; Cacho Teixeira, IMC; Cacho Teixeira, JPC; Vargas, F. 2013. "Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs". IEEE TRANSACTIONS ON NANOTECHNOLOGY. https://doi.org/10.1109/tnano.2013.2253795
Romão, André Azevedo de Sousa. 2013. "Dynamic power and frequency optimization in digital electronic systems". Mestrado. http://hdl.handle.net/10400.1/5990
Coelho, João Ricardo dos Santos. 2013. "Aging monitoring methodology for built-In self-test applications". Mestrado. http://hdl.handle.net/10400.1/6899
Pachito, J; Martins, CV; Semiao, J; Santos, M; Teixeira, IC; Teixeira, JP. 2012. "The Influence of Clock-Gating On NBTI-Induced Delay Degradation". https://doi.org/10.1109/iolts.2012.6313842
Freijedo, J.F.; Semiäo, J.; Rodriguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2012. "Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits". Journal of Electronic Testing: Theory and Applications (JETTA), 28 (4): 421-434. https://doi.org/10.1007/s10836-012-5297-0
Pachito, J.; Martins, C.V.; Jacinto, B.; Semião, J.; Vazquez, J.C.; Champac, V.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. 2012. "Aging-aware power or frequency tuning with predictive fault detection". IEEE Design and Test of Computers, 29 (5): 27-36. https://doi.org/10.1109/MDT.2012.2206009
Pachito, J.; Martins, C.V.; Semiao, J.; Santos, M.; Teixeira, I.C.; Teixeira, J.P.. 2012. "The influence of clock-gating on NBTI-induced delay degradation". Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium, IOLTS 2012, 61-66. https://doi.org/10.1109/IOLTS.2012.6313842
Pachito, J; Martins, CV; Jacinto, B; Teixeira, IC; Teixeira, JP; Semiao, J; Vazquez, JC; Champac, V; Santos, MB. 2012. "Aging-Aware Power or Frequency Tuning With Predictive Fault Detection". IEEE DESIGN & TEST OF COMPUTERS. https://doi.org/10.1109/mdt.2012.2206009
Pachito, Jakson dos Santos. 2012. "Metodologia para prever o envelhecimento de circuitos digitais". Mestrado. http://hdl.handle.net/10400.1/3250
Martins, Celestino Virtudes Dias. 2012. "Adaptive error-prediction aging sensor for synchronous digital circuits". Mestrado. http://hdl.handle.net/10400.1/3280
Valdes, M; Freijedo, J; Moure, MJ; Rodriguez Andina, JJ; Semiao, J; Vargas, F; Teixeira, IC; Teixeira, JP. 2011. "Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects". https://doi.org/10.1109/latw.2011.5985926
Oliveira, RS; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP. 2011. "On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications". https://doi.org/10.1109/latw.2011.5985919
Freijedo, J; Semiao, J; Rodriguez Andina, JJ; Vargas, F; Teixeira, IC; Teixeira, JP. 2011. "Modeling the effect of process variations on the timing response of nanometer digital circuits". https://doi.org/10.1109/latw.2011.5985927
Bexiga, V; Leong, C; Semiao, J; Teixeira, I; Teixeira, JP; Valdes, M; Freijedo, J; Rodriguez Andina, JJ; Vargas, F. 2011. "Performance failure prediction using built-in delay sensors in FPGAs". https://doi.org/10.1109/fpl.2011.61
Martins, CV; Semiao, J; Vazquez, JC; Champac, V; Santos, M; Teixeira, IC; Teixeira, JP. 2011. "Adaptive Error-Prediction Flip-flop for Performance Failure Prediction with Aging Sensors". https://doi.org/10.1109/vts.2011.5783784
Silva, D.; Poehls, L.B.; Semião, J.; Teixeira, I.C.; Teixeira, J.P.; Valdés, M.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.. 2011. "IP core to leverage RTOS-based embedded systems reliability to electromagnetic interference". Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011, 119-124. http://www.scopus.com/inward/record.url?eid=2-s2.0-84856994091&partnerID=MN8TOARS
Oliveira, R.S.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. 2011. "On-line BIST for performance failure prediction under NBTI-induced aging in safety-critical applications". Journal of Low Power Electronics, 7 (4): 562-572. https://doi.org/10.1166/jolpe.2011.1155
Bexiga, V.; Leong, C.; Semião, J.; Teixeira, Ic.; Teixeira, J.P.; Valdés, M.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.. 2011. "Performance failure prediction using built-in delay sensors in FPGAs". Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, 301-304. https://doi.org/10.1109/FPL.2011.61
Freijedo, J.; Semião, J.; Rodríguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2011. "Modeling the effect of process variations on the timing response of nanometer digital circuits". LATW 2011 - 12th IEEE Latin-American Test Workshop. https://doi.org/10.1109/LATW.2011.5985927
Valdés, M.; Freijedo, J.; Moure, M.J.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2011. "Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects". LATW 2011 - 12th IEEE Latin-American Test Workshop. https://doi.org/10.1109/LATW.2011.5985926
Oliveira, R.S.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. 2011. "On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications". LATW 2011 - 12th IEEE Latin-American Test Workshop. https://doi.org/10.1109/LATW.2011.5985919
Martins, C.V.; Semião, J.; Vazquez, J.C.; Champac, V.; Santos, M.; Teixeira, I.C.; Teixeira, J.P.. 2011. "Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors". Proceedings of the IEEE VLSI Test Symposium, 203-208. https://doi.org/10.1109/VTS.2011.5783784
Freijedo, J.; Valdés, M.D.; Costas, L.; Moure, M.J.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2011. "Lower V DD operation of FPGA-based digital circuits through delay modeling and time borrowing". Journal of Low Power Electronics, 7 (2): 185-198. https://doi.org/10.1166/jolpe.2011.1127
Vazquez, JC; Champac, V; Ziesemer, AM; Reis, R; Semiao, J; Teixeira, IC; Santos, MB; Teixeira, JP. 2010. "Predictive error detection by on-line aging monitoring". https://doi.org/10.1109/iolts.2010.5560241
Chipana, R; Bolzani, L; Vargas, F; Semiao, J; Rodriguez Andina, J; Teixeira, I; Teixeira, P. 2010. "Investigating the use of BICS to detect resistive- open defects in SRAMs". https://doi.org/10.1109/iolts.2010.5560207
Freijedo, JF; Valdes, MD; Moure, MJ; Costas, L; Rodriguez Andina, JJ; Semiao, J; Vargas, F; Teixeira, IC; Teixeira, JP. 2010. "Delay modeling for power noise-aware design in Spartan-3A FPGAS". https://doi.org/10.1109/spl.2010.5483026
Chipana, R.; Bolzani, L.; Vargas, F.; Semião, J.; Rodríguez-Andina, J.; Teixeira, I.; Teixeira, P.. 2010. "Investigating the use of BICS to detect resistive- open defects in SRAMs". Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010, 200-201. https://doi.org/10.1109/IOLTS.2010.5560207
Vazquez, J.C.; Champac, V.; Ziesemer Jr., A.M.; Reis, R.; Semião, J.; Teixeira, I.C.; Santos, M.B.; Teixeira, J.P.. 2010. "Predictive error detection by on-line aging monitoring". Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010, 9-14. https://doi.org/10.1109/IOLTS.2010.5560241
Freijedo, J.; Costas, L.; Semião, J.; Rodríguez-Andina, J.J.; Moure, M.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2010. "Impact of power supply voltage variations on FPGA-based digital systems performance". Journal of Low Power Electronics, 6 (2): 339-349. https://doi.org/10.1166/jolpe.2010.1076
Freijedo, J.F.; Valdés, M.D.; Moure, M.J.; Costas, L.; Rodríguez-Andina, J.J.; Semião, J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2010. "Delay modeling for power noise-aware design in Spartan-3A FPGAS". 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings, 127-132. https://doi.org/10.1109/SPL.2010.5483026
Semiao, J; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C; Benfica, J; Vargas, F; et al. 2009. "Measuring Clock-Signal Modulation Efficiency for Systems-on-Chip in Electromagnetic Interference Environment". https://doi.org/10.1109/latw.2009.4813817
Semiao, J; Freijedo, J; Rodriguez Andina, J; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. 2009. "Delay-Fault Tolerance to Power Supply Voltage Disturbances Analysis in Nanometer Technologies". https://doi.org/10.1109/iolts.2009.5196020
Semião, J.; Freijedo, J.; Rodriguez-Andina, J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. 2009. "Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies". 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009, 223-228. https://doi.org/10.1109/IOLTS.2009.5196020
Semiao, J.; Freijedo, J.; Moraes, M.; Mallmann, M.; Antunes, C.; Benfica, J.; Vargas, F.; et al. 2009. "Measuring clock-signal modulation efficiency for systems-on-chip in electromagnetic interference environment". 2009 10th Latin American Test Workshop, LATW 2009. https://doi.org/10.1109/LATW.2009.4813817
Semiao, J; Varela, J; Freijedo, J; Andina, J; Leong, C; Teixeira, JP; Teixeira, I. 2008. "Robust Solution for Synchronous Communication among Multi Clock Domains". https://doi.org/10.1109/apccas.2008.4746218
Semiao, J; Freijedo, J; Moraes, M; Mallmann, M; Antunes, C; Rocha, L; Benfica, J; et al. 2008. "Power-Supply Instability Aware Clock Signal Modulation for Digital Integrated Circuits". https://doi.org/10.1109/emceurope.2008.4786876
Semiao, J; Rodriguez Andina, JJ; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. 2008. "Process tolerant design using thermal and power-supply tolerance in pipeline based circuits". https://doi.org/10.1109/ddecs.2008.4538752
Semiao, J; Freijedo, J; Andina, J; Vargas, F; Santos, M; Teixeira, I; Teixeira, P. 2008. "Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits". https://doi.org/10.1109/iolts.2008.51
Freijedo, J.F.; Semião, J.; Rodríguez-Andina, J.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.. 2008. "Delay modeling for power noise and temperature-aware design and test of digital systems". Journal of Low Power Electronics, 4 (3): 385-391. https://doi.org/10.1166/jolpe.2008.191
Semião, J.; Freijedo, J.; Moraes, M.; Mallmann, M.; Antunes, C.; Rocha, L.; Benfica, J.; et al. 2008. "Power-supply instability aware clock signal modulation for digital integrated circuits". IEEE International Symposium on Electromagnetic Compatibility. https://doi.org/10.1109/EMCEUROPE.2008.4786876
Semião, J.; Freijedo, J.F.; Rodriguez-Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. 2008. "Time Management for Low-Power Design of Digital Systems". Journal of Low Power Electronics, 4 (3): 410-419. https://doi.org/10.1166/jolpe.2008.194
Semião, J.F.L.C.; Irago, M.J.R.; Rodrïuez-Andina, J.J.; Piccoli, L.B.; Vargas, F.L.; dos Santos, M.B.; Teixeira, I.M.C.; Teixeira, J.P.. 2008. "Signal integrity enhancement in digital circuits". IEEE Design and Test of Computers, 25 (5): 452-461. https://doi.org/10.1109/MDT.2008.146
Semião, J.; Freijedo, J.; Andina, J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. 2008. "Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits". Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008, 227-232. https://doi.org/10.1109/IOLTS.2008.51
Semião, J.; Rodriguez-Andina, J.J.; Vargas, F.; Santos, M.; Teixeira, I.; Teixeira, P.. 2008. "Process tolerant design using thernal and power-supply tolerance in pipeline based circuits". Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 34-37. https://doi.org/10.1109/DDECS.2008.4538752
Semiao, JFLC; Rodriguez Irago, MJR; Rodriguez Andina, JJ; Piccoli, LB; Vargas, FL; dos Santos, MB; Cacho Teixeira, IMC; Teixeira, JP. 2008. "Signal integrity enhancement in digital circuits". IEEE DESIGN & TEST OF COMPUTERS. https://doi.org/10.1109/mdt.2008.146
Semião, J.; Freijedo, J.; Andina, J.; Varela, J.; Leong, C.; Teixeira, J.P.; Teixeira, I.. 2008. "Robust solution for synchronous communication among multi clock domains". IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 1107-1110. https://doi.org/10.1109/APCCAS.2008.4746218
Semiao, J; Freijedo, J; Andina, JJR; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. 2007. "Enhancing the tolerance to power-supply instability in digital circuits". https://doi.org/10.1109/isvlsi.2007.44
Semiao, J; Freijedo, J; Rodiriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. 2007. "Improving tolerance to power-supply and temperature variations in synchronous circuits". https://doi.org/10.1109/ddecs.2007.4295299
Semiao, J; Freijedo, J; Rodriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. 2007. "On-line dynamic delay insertion to improve signal integrity in synchronous circuits". https://doi.org/10.1109/iolts.2007.49
Semiao, J; Rodriguez Andina, JJ; Vargas, F; Santos, MB; Teixeira, IC; Teixeira, JP. 2007. "Improving the tolerance of pipeline based circuits to power supply or temperature variations". https://doi.org/10.1109/dft.2007.60
Semião, J.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. 2007. "Improving tolerance to power-supply and temperature variations in synchronous circuits". Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 295-300. https://doi.org/10.1109/DDECS.2007.4295299
Semião, J.; Freijedo, J.; Rodríguez-Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. 2007. "On-line dynamic delay insertion to improve signal integrity in synchronous circuits". Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium, 167-172. https://doi.org/10.1109/IOLTS.2007.49
Semiao, J.; Rodriguez-Andina, J.J.; Vargas, F.; Santos, M.B.; Teixeira, I.C.; Teixeira, J.P.. 2007. "Improving the tolerance of pipeline based circuits to power supply or temperature variations". Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 303-311. https://doi.org/10.1109/DFT.2007.60
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